Verification Engineers

Gratitude Inc

538 Views

17 hours ago

3-6 Year(s)

₹ 14 - ₹ 16 Thousand p.a

Chanod

Job Description

Key Skills

Verilog RTL Design Verification IPs SystemVerilog SV-UVM OVM Verification engineer

1 candidate(s) have already applied for this Job. Apply now

Description / Requirements

Designation: Verification Engineer

Exp: 3-6 yrs

Location: Hanoi, Vietnam

CTC: As per the CDD’s Exp & Skillset

Social health and unemployment insurance benefits will be provided

Shift Timings: 8:30 am - 5:30 pm

Need immediate joiners and Local Candidates only

Job Description:

Experience in RTL Functional Verification using SystemVerilog, SV-UVM, OVM.

Experience in Developing Verification IPs.

Experience in writing Synthesizable Testbench and preformed Emulation.

Experience in coding using C, C++, Python, TCL, Perl, etc.

Experience in Video, Networking, and LTE/5G Domains is an added advantage.

Experience in SoC verification from test planning till tape-out is added advantage.

Good Knowledge of various protocols and bus standards like PCI, PCIe, Ethernet, USB, DDR-SDRAM, IIC, SPI, AXI, Avalon,

Role

Program Manager

Timings

Day Shift (Permanent)

Industry

IT-Software / Software Services

Work Mode

Process

Chat

Functional Area

IT Software/Hardware

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